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DATA BULLETIN
MX803A
Features
* Full Duplex Audio Signaling Processor Single Tone Selective Call systems * Tone Decoder with programmable NOTONE timer. * Two Individual tone encoders and a programmable TX Period Timer. * Low Power CMOS Device * On-Chip programmable amplifier. * C-BUS Compatible
SIGNAL INPUT BIAS DIGITAL NOISE FILTER 1
RX FILTER SWITCH
Audio Signaling Processor
PRELIMINARY INFORMATION
Applications
* Signaling Systems supported SelCall (CCIR, EEA, ZVEI I / II /III) 2-Tone SelCall DTMF Encode * Inband Tone Signaling capability for LMR and other Radio Systems.
(RX) AUDIO IN
DIGITAL NOISE FILTER 2
COMMAND DATA
QUALITY METER
PROGRAMMABLE NOTONE TIMER
REPLY DATA
GATE TIME GENERATOR
C-BUS INTERFACE AND CONTROL LOGIC
CHIP SELECT INTERRUPT SERIAL CLOCK LOGIC INPUT
FREQUENCY COUNTER
VDD
PROGRAMMABLE (TX PERIOD) TIMER
VBIAS
TONE 1 GENERATOR 5-/2-TONE DTMF 1
LOW PASS FILTER
TONE 1 OUT
SUM IN SWITCHED SUM OUT
VSS _ VBIAS XTAL/ CLOCK XTAL AUDIO SWITCH IN
AUDIO SWITCH
SUMMING SWITCH
SUM OUT CAL/CUES OUT
+ SUMMING AMPLIFIER
CUES
CAL/CUES SWITCH
CLOCK GENERATOR
CAL
TONE 2 GENERATOR CUES/DTMF 2
LOW PASS FILTER
TONE 2 OUT
SWITCH OUT
The MX803A is an audio signaling processor that provides inband tone signaling capabilities for LMR and other Radio systems. A low-power CMOS device, the MX803A is a member of the DBS800 (Digitally integrated Baseband Subsystem) IC family (See section 4.2). Supported Signaling systems include SelCall (CCIR, EEA, ZVEI I, II, and III) 2-Tone SelCall and DTMF encode. The use of a non-predictive decoder and a versatile encoder, allows the MX803A to operate in any standard or non-standard tone system. The MX803A is a full-duplex device for use with Single Tone or Selective Call systems. The MX803A consists of a tone decoder with a programmable NOTONE timer, two individual tone encoders and a programmable TX period timer, and an on-chip summing amplifier. Under the control of a C, the MX803A will simultaneously encode and transmit 1 or 2 audio tones in the 208-3000Hz range, as well as detect, decode, and indicate the frequency of any non-predicted input tone in the frequency range of 313 to 6000Hz. The MX803A is available in 24-pin CDIP (MX803AJ), 24-pin PLCC (MX803ALH), and 24-pin SOIC (MX803ADW) packages.
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MX803A PRELIMINARY INFORMATION
CONTENTS
Section Page
1. Block Diagram .................................................................................................................................. 3 2. Signal List ......................................................................................................................................... 4 3. External Components ...................................................................................................................... 6 4. General Description ......................................................................................................................... 7
4.1 DESCRIPTION.......................................................................................................................................... 7 4.2 DBS800 Systems ...................................................................................................................................... 7 4.3 C-BUS Control .......................................................................................................................................... 8
5. Application ....................................................................................................................................... 8
5.1 MX803A Internal Registers ....................................................................................................................... 8 5.2 Address/Commands.................................................................................................................................. 9 5.3 Powersave ............................................................................................................................................... 18 5.4 Interrupt Request IRQ .............................................................................................................................. 19 5.5 Operational Recommendations................................................................................................................ 19 5.6 General Reset .......................................................................................................................................... 20
6. Timing Information.......................................................................................................................... 20 7. Performance Specification............................................................................................................. 22
7.1 Electrical Performance ............................................................................................................................. 22 7.2 Packaging ................................................................................................................................................ 25
MX*COM, Inc. reserves the right to change specifications at any time and without notice.
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MX803A PRELIMINARY INFORMATION
1. Block Diagram
SIGNAL INPUT BIAS DIGITAL NOISE FILTER 1
RX FILTER SWITCH
(RX) AUDIO IN
DIGITAL NOISE FILTER 2
COMMAND DATA
QUALITY METER
PROGRAMMABLE NOTONE TIMER
REPLY DATA
GATE TIME GENERATOR
C-BUS INTERFACE AND CONTROL LOGIC
CHIP SELECT INTERRUPT SERIAL CLOCK LOGIC INPUT
FREQUENCY COUNTER
VDD
PROGRAMMABLE (TX PERIOD) TIMER
VBIAS
TONE 1 GENERATOR 5-/2-TONE DTMF 1
LOW PASS FILTER
TONE 1 OUT
SUM IN SWITCHED SUM OUT
VSS _ VBIAS XTAL/ CLOCK XTAL AUDIO SWITCH IN
AUDIO SWITCH
SUMMING SWITCH
SUM OUT CAL/CUES OUT
+ SUMMING AMPLIFIER
CUES
CAL/CUES SWITCH
CLOCK GENERATOR
CAL
TONE 2 GENERATOR CUES/DTMF 2
LOW PASS FILTER
TONE 2 OUT
SWITCH OUT
Figure 1: Block Diagram
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MX803A PRELIMINARY INFORMATION
2. Signal List
Pin No. 1 2 3 Name
XTAL
Type
Description
Output Output of the on-chip clock oscillator. External components are required at this output when a Xtal is used. See Figure 2. Input Input to the on-chip clock oscillator inverter. A Xtal or externally derived clock should be connected here. See Figure 2.
Xtal/Clock Reply Data
Output C-BUS serial data output to the C. The transmission of Reply Data bytes is synchronized to the Serial Clock under the control of the Chip Select input. This 3-state output is held at high impedance when not sending data to the C. See Figure 8 and Figure 9. Input C-BUS data loading control function. This input is provided by the C. Data transfer sequences are initiated, completed or aborted by the chip select signal. See Figure 8 and Figure 9. C-BUS serial data input from the C. Data is loaded to this device in 8-bit bytes, MSB (B7) first and LSB (B0) last, synchronized to the Serial Clock. See Figure 8 and Figure 9. This "real-time" input is available as a general purpose logic input port which can be read from the Status Register. See Table 3. G/Purpose Timer Period Expired NOTONE Timer Period Expired RX Tone Measurement Complete These interrupts are inactive during relevant powersave conditions and can be disabled by bits 5 and 6 in the Control Register.
4
CS
5
Command Data
Input
6
Logic Input
Input
7
IRQ
Output Output of this pin indicates an interrupt condition to the C by going to a logic "0." This is a "wire-or-able" output, allowing the connection of up to 8 peripherals to 1 interrupt port on the C. This pin has a low impedance pulldown to logic "0" when active and a high impedance when inactive. The system IRQ line requires one pullup resistor to VDD. The conditions that cause interrupts are indicated in the Status Register and are shown below: Input Input to the stand-alone on-chip Audio Switch. This function is enabled/disabled by Bit 7 of the Control Register Negative supply (GND). Received audio tone signaling input. This input must be ac coupled and connected, using external components, to the Signal Input Bias pin. See Figure 2. External components are required between this input and the RX Audio In pin. See Figure 2.
10 11 12 13
Audio Switch In Audio Switch Out VSS Rx Audio In
Output Output of the stand-alone on-chip Audio Switch.. Power Input
14 15 16
Signal Input Bias VBIAS Tone 1 Out
Input
Output Internal circuitry bias signal, held at VDD/2. This pin should be decoupled to VSS by capacitor C2. See Figure 2.. Output Tone 1 Generator (2-/5-tone Selcall or DTMF 1) output. External gain and coupling components are required at this output when operating in a complete DBS 800 audio installation. The frequency of this output is determined by writing to the TX Tone Generator 1 Register (Table 5). See Figure 2. Output Tone 2 Generator (2-/5-tone Selcall, CUES or DTMF 2) output. External gain and coupling components are required at this output when operating in a complete DBS 800 audio installation. The frequency of this output is determined by writing to the TX Tone Generator 2 Register (Table 5). See Figure 2.
17
Tone 2 Out
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MX803A PRELIMINARY INFORMATION
Pin No. 18
Name CAL/CUES Out
Type
Description
Output An auxiliary, selectable tone frequency output, providing a square wave CALibration signal from the Tone 2 Generator or a sine wave CUES (beep) signal from the Summing Amplifier. The output mode (CAL or CUES) is selected by Bit 14 in the TX Tone Generator 2 Register (Table 5). When Tone Generator 2 is set to Notone, the CAL input is pulled to VBIAS; during a powersave of Tone Generator 2 it is held at VSS. Input Input to the on-chip Summing Amplifier. This amplifier is available for combining Tone 1 and Tone 2 outputs (DTMF). Gain and coupling components should be used at this input to provide the required system gains. See Figure 2 and Figure 3
19
Sum in
20 21
Sum Out Switched Sum Out Serial Clock
Output Output of the on-chip summing amplifier. Combined tones (1 and 2) are available at this output. See Figure 2 and Figure 3. Output This is the combined tone output available for transmitter modulation. The switch allows control of the MX803A output. Control of this switch is by Bit 4 of the Control Register. See Figure 2 and Figure 3. Input C-BUS serial clock input. This clock, produced by the C, is used for transfer timing of commands and data to and from the MX803A. See Figure 8 and Figure 9. Positive supply. A single +5 volt power supply is required. Levels and voltages within this Audio Signaling Processor are dependent upon this supply.. No Internal Connection. These pins may be connected to VSS to improve screening and reduce noise levels around the MX803A.
23
24 8, 9, 22
VDD N/C
Power
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MX803A PRELIMINARY INFORMATION
3. External Components
VDD
SEE INSET BELOW
XTAL XTAL/CLOCK REPLY DATA CS
COMMAND DATA LOGIC INPUT IRQ
AUDIO SWITCH IN AUDIO SWITCH OUT R7 VSS
1 2 3 4 5 6 7 8 9 10 11 12
MX803A
24 23 22 21 20 19 18 17 16 15 14 13
VBIAS SERIAL CLOCK SWITCHED SUM OUT SUM OUT SUM IN R3 R4 R5 R2 C2 C1 CAL/CUES OUT TONE 2 OUT TONE 1 OUT VBIAS SIGNAL BIAS RX AUDIO IN R6 C5 TONE LEVEL AND GAIN COMPONENTS C6
INSET
XTAL
1
X1 C4
R1
MX803A 2
C3
XTAL/CLOCK
R1 R2 R3 R4 R5 R6 R7 Note 2, 3 Note 2, 3 Note 2, 3 Note 2 Note 2, 5
1.0M 2.0M 100k 82.0k 122k 100k 100k
10% 10% 10% 10% 10% 10% 10%
C1 C2 C3 C4 C5 C6 X1 Note 1, 4 Note 4 Note 4 Note 3
0.1F 1.0F 33.0pF 33.0pF 22.0pF 1.0F 4.00MH z
20% 20% 20% 20% 20% 20%
Figure 2: Recommended External Components Notes: 1. Xtal/clock components described are recommended in accordance with MX-COM's Application Note on Standard and DBS 800 Crystal Oscillator Circuits (April 1990). For best results, a crystal oscillator design should drive the clock inverter input with signal levels of at least 40% of VDD, peak to peak. Tuning fork crystals generally cannot meet this requirement. To obtain crystal oscillator design assistance, consult your crystal manufacturer. 2. System Components whose values are calculated to allow the MX803A to operate with other DBS 800 microcircuits. Figure 3 shows these components used in the system signal paths. 3. R3, R4, R5 and C5 are tone mixing components calculated to provide a 3dB tone differential (twist) for use in a DTMF configuration. Single tone output levels are set independently. 4. When X1 > 5.00MHz, C3 = C4 = 18pF 5. R7 provides modulation level and matching outputs for the MX803A.
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MX803A PRELIMINARY INFORMATION
FROM MX806A MAIN PROCESS OUT AUDIO SWITCH OUT
AUDIO SWITCH IN
TO MX806A SUM IN
MX803A
11
18 CAL/CUES OUT
CAL CUES TONE 2 OUT TO MX806A CALIBRATION IN
21
SWITCHED SUM OUT
17 16
BIAS 19
+ _
SUMMING AMPLIFIER
20 SUM OUT
TONE 1 OUT
SUM IN
Figure 3: Example of Signal Switching in a DBS800 microcircuit
4. General Description
4.1 DESCRIPTION
The MX803A is an audio signaling processor that provides inband tone signaling capabilities for LMR and other Radio systems. A low-power CMOS device, the MX803A is a member of the DBS800 (Digitally integrated Baseband Subsystem) IC family (See section 4.2). Supported Signaling systems include SelCall (CCIR, EEA, ZVEI I, II, and III) 2-Tone SelCall and DTMF encode. The use of a non-predictive decoder and a versatile encoder, allows the MX803A to operate in any standard or non-standard tone system. The MX803A is a full-duplex device for use with Single Tone or Selective Call systems. The MX803A consists of a tone decoder with a programmable NOTONE timer, two individual tone encoders and a programmable TX period timer, and an on-chip summing amplifier. Under the control of a C, the MX803A will simultaneously encode and transmit 1 or 2 audio tones in the 208-3000Hz range, as well as detect, decode, and indicate the frequency of any non-predicted input tone in the frequency range of 313 to 6000Hz. A general purpose logic input, interfacing directly with the Status Register, is provided. This may be used as an auxiliary method of routing digital information to the C via C-BUS. Output frequencies are produced from data loaded to the MX803A. A programmable, general purpose, on-chip timer sets the tone transmit periods. A Dual-Tone Multi-Frequency (DTMF) output is obtained by combining the 2 independent output frequencies in the integral summing amplifier. This process can also be used for level correction. Tones produced by the MX803A can be used in the system as modulation calibration inputs and as "CUE" audio indications to the operator. Received tones are measured and their frequency indicated to the C in the form of a received data word. A poor quality or incoherent tone will indicate Notone.
4.2 DBS800 Systems
The Digitally-Integrated Baseband Subsystem (DBS800) is a family of low power ICs which provide a comprehensive range of audio processing and signaling functions for use within LMR and other Radio Systems. Each DBS800 IC may be used as part of a complete audio system, or each IC may operate as a stand alone. The system and ICs are partitioned in such a way that radio designers can easily select the device or devices appropriate to their needs. The DBS800 family consists of the following ICs: 4.2.1 MX802 DVSR Codec This is a full-duplex CVSD speech encoder/decoder with the ability to store and retrieve data within attached DRAM (Dynamic Random Access Memory) using an on-chip DRAM controller. The MX802 also provides on-chip input and output audio filtering. 4.2.2 MX803A Audio Signaling Processor This provides an inband tone signaling ability to LMR and other Radio Systems.
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DBS 800 TRANSMIT AUDIO BUS
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MX803A PRELIMINARY INFORMATION
4.2.3 MX805A Sub-Audio Signaling Processor This provides a sub-audio and digital signaling (NRZ) ability to LMR and other Radio Systems. 4.2.4 MX806A Audio Processor This is a half duplex audio processor providing all DBS800 system audio signal conditioning and filtering capabilities for the system transmit and receive paths. 4.2.5 MX809 MSK Modem This is an intelligent, half-duplex 1200bps MSK/FFSK Modem with software programmable byte-synchronization system and checksum generation and checking. 4.2.6 MX812 VSR Codec This is a half-duplex CVSD speech encoder/decoder with the ability to store and retrieve data within attached DRAM (Dynamic Random Access Memory) using an on-chip DRAM controller
4.3 C-BUS Control
C-BUS is the controlling hardware and software interface for all members of the DBS800 family. It enables the serial, bidirectional transfer of commands and data throughout the system, allowing total flexibility of operational control and data handling. System upgrades can be achieved by a simple software or firmware change. The C-BUS physically consist of 5 lines. These lines are Serial Clock, Command Data, Reply Data, Chip Select ( CS ), and Interrupt Request ( IRQ ). A description of each may be found in section 2.
5. Application
Control of the MX803A Audio Signaling Processor's operation is by communication between the C and the MX803A internal registers on the C-BUS using Address/Commands (A/Cs) and appended instructions or data. See Figure 8. The use and content of these instructions is detailed in the following sections. For additional application information contact MX*COM, Inc.
5.1 MX803A Internal Registers
Control Register Status Register RX Tone Frequency Register RX Notone Timer TX Tone Generator 1 Register TX Tone Generator 2 Register General Purpose Timer Register 30H 31H 32H 33H 34H 35H 36H Write only, control and configuration of the MX803A. Read only, reporting of device functions. Read only, indicates frequency of the last received input. Write only, setting of the RX Notone period. Write only, setting the required output frequency from TX Tone Generator 1. Write only, setting the required output frequency from TX Tone Generator 2. Write only, setting of a general purpose sequential time period.
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MX803A PRELIMINARY INFORMATION
5.2 Address/Commands
The first byte of a loaded data sequence is always recognized by the C-BUS as an Address/Command (A/C) byte. Instruction and data transactions to and from this device consist of an A/C byte followed by further instruction/data or a status/data reply. Instructions and data are loaded and transferred via C-BUS in accordance with the timing information given in Figure 8 and Figure 9. Table 1 shows the list of A/C bytes relevant to the MX803A. Command Assignment Address/Command (A/C) Byte Data Bytes Hex msb General Reset Write to Control Register Read Status Register Read RX Tone Frequency Write to Notone Timer Write to TX Tone Gen. 1 Write to TX Tone Gen. 2 Write to G/Purpose Timer 01 30 31 32 33 34 35 36 Binary lsb + 1 byte instruction to Control Register + 1 byte reply from Status Register + 2 bytes reply from RX Tone Register + 1 byte instruction to Notone Register + 2 bytes instruction to TX Tone Gen. 1 + 2 bytes instruction to TX Tone Gen. 2 + 1 byte instruction to G/Purpose Timer 00000001 00110000 00110001 00110010 00110011 00110100 00110101 00110110
Table 1: C-BUS Address/Commands
0
1000
2000
3000
4000
5000
6000
(TX) Tone Generators 1 and 2
1250Hz to 6000Hz
208Hz to 3000Hz
(RX) Extended Band (RX) High Band
625Hz to 3000Hz
(RX) Mid Band
0 1000
313Hz to 1500Hz
2000 3000 4000 5000 6000
Frequency (Hz)
Figure 4: MX803A Frequencies
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MX803A PRELIMINARY INFORMATION
5.2.1 Write to Control Register A/C 30H, followed by 1 byte of Command Data Audio Switch: General Purpose Timer: Interrupt Enable Instructions: Band Selection: Summing Switch: Interrupt Designation: Enables or Disables the stand-alone on-chip Audio Switch. This should be set up before interrupts are enabled since a General Reset command will set the timer period to 00H - 0ms (permanent interrupt). Status bits 0, 1 and 2 are produced regardless of the state of these settings. Bits 2 and 3 set the required frequency range. See Figure 4. Used to Enable or Disable the switch that controls the MX803A output. Decoder Interrupts Notone Timer and RX Tone Measurement Transmitter Interrupt G/Purpose Timer Interrupt
Setting MSB Bit 7 1 0 Bit 6 1 0 Bit 5 1 0 Bit 4 1 0 Bit 3 0 0 1 1 Bit 1 0 Bit 0 0 Bit 2 0 1 0 1 Control Bits Transmitted First Audio switch Enable Disable G/Purpose Timer Interrupt Enable Disable Decoder Interrupts Enable Disable Summing Switch Enable Disable Band Selection High Band Mid Band Extended Band Do not use this setting Set to 0 Set to 0
Table 2: Control Register
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MX803A PRELIMINARY INFORMATION
5.2.2 Read Status Register A/C 31H, followed by 1 byte of Reply Data Interrupt Requests (IRQ): Interrupts on this device are available to draw the attention of the C to a change in the condition of the bit in the status register. However, bits are set in the status register irrespective of the setting of interrupt enable bits (Table 2) and these changes may be recognized by polling the register. General Purpose Timer Period: Set to a logic "1" when the timer period has expired. Cleared to a logic "0" by: 1. Reading the Status Register 2. New G/Purpose Timer information 3. General Reset command Notone Timer Period: Set to a logic "1" when the timer period has expired. Cleared to a logic "0" by: 1. Reading the Status Register 2. New Notone Timer information 3. General Reset command RX Tone Measurement: Set to a logic "1" when the RX Tone Measurement is complete. Cleared to a logic "0" by: 1. Reading the Status Register 2. General Reset command
Setting MSB Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 1 0 Bit 2 1 Bit 1 1 Bit 0 1 Status Bits Received First Set to 0 Set to 0 Set to 0 Set to 0 Logic Input Status 1 0 G/Purpose Timer Period Expired (Interrupt Generated) Notone Timer Period Expired (Interrupt Generated) RX Tone Measurement Complete (Interrupt Generated)
Table 3: Status Register
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MX803A PRELIMINARY INFORMATION
5.2.3 TX Tone Generator Registers 1 and 2 Each TX Tone Generator is controlled individually by writing a two-byte command to the relevant TX Tone Generator Register. The format of this command word, which is different for each tone generator, is shown below with the calculations required for tone frequency (fTONE) generation described in the following text. 5.2.3.1 Write to TX Tone Generator 1 Register A/C 34H, followed by 2 bytes of Command Data MSB (loaded first) 15 0 14 0 13 Notone/Enable 12 Bit Numbers 11 10 9 8 7 6 5 4 3 LSB (loaded last) 2 1 0
These 13 bits (0 to 12) are used to produce a binary number, designated `A'. `A' is used in the formulas below to set the TX Tone 1 frequency (fTONE1). Table 4: Tx Tone Generator 1
5.2.3.1.1 SETTING TX TONE GENERATOR 1 The binary number produced by Bits 0 to 12 (MSB) is designated "A." If "A" = all logic "0" TX Tone Generator 1 is Powersaved. Bit 13 at logic 1 0 = = Tone 1 Output at VBIAS (NOTONE) Tone 1 Output Enabled
Bits14 and15(MSB) must be logic 0 5.2.3.2 Write to TX Tone Generator 2 Register A/C 35H, followed by 2 bytes of Command Data MSB (loaded first) 15 0 14 CAL/CUES 13 Notone/Enable 12 11 Bit Numbers 10 9 8 7 6 5 4 3 2 LSB (loaded last 1 0
These 13 bits (0 to 12) are used to produce a binary number, designated `B'. `B' is used in the formulas below to set the TX Tone 2 frequency (fTONE2). Table 5: Tx Tone Generator 2
Write to TX Tone Generator 2 Register Notes: Programming Tone Generator 2 to Notone will place the CAL/CUES output at VBIAS via a 40k internal resistor. Programming Tone Generator 2 to Powersave will place the CAL/CUES output at VSS. If both Tone Generators are Powersaved, the Input Amplifier is also Powersaved 5.2.3.2.1 SETTING TX TONE GENERATOR 2 The binary number produced by bits 0 to 12 (MSB) is designated "B." If "B" = all logic "0" then TX Tone Generator 2 is Powersaved. Bit 13 at logic 1 = Tone 1 Output at VBIAS (NOTONE) 0 = Tone 1 Output Enabled Bit 14 at logic 1 = Squarewave CAL Output 0 = Sinewave CUES Output Bit 15 (MSB) must be a logic "0."
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MX803A PRELIMINARY INFORMATION
5.2.3.3 Calculations As seen in Table 4 and Table 5, a binary number ("A" or "B" - bits 0 to 12) is loaded to the respective TX Tone Generator. The formulas described below are used to produce the required output frequency. Required TX Tone output frequency Xtal/clock frequency Input Data Word (bits 0 to 12) f TONE = 5.2.3.4 Tx Tone Frequencies With reference to Table 4 and Table 5, while Input Data Words "A" or "B" can be programmed for frequencies outside the stated limits of 208Hz and 3000Hz, any output frequencies obtained may not be within specified parameters. See section 7. 5.2.4 Read RX Tone Frequency Register A/C 32H, followed by 2 bytes of Reply Data 5.2.4.1 Measurement of RX Signal Frequency SIN The input audio signal, S , is measured in the Frequency Counter over a specified measurement period (9.125ms or IN 18.250ms). The measuring function counts the number of complete input cycles occurring within the count period and then the number of measuring clock cycles necessary to make up the period. When the count period of a successful decode is complete, the RX Tone Measurement bit in the Status Register and the Interrupt bit are set. The RX Tone Frequency Register will now indicate the signal frequency S in the form of 2 bytes (1 and 0) as illustrated IN in Figure 6. Note: The following measurements are based on a clock frequency of 4.032 MHz. See section 5.2.4.4 for a scaling formula for other crystal values).
Measurement Period
Complete Input Cycle Complete Input Cycle Complete Input Cycle Complete Input Cycle Complete Input Cycle
Measuring Clock Cycles
= = =
fTONE 1 or 2 fXTAL "A" or "B" or Input ' A' or 'B' = f XTAL Hz 4 x f TONE
f XTAL Hz 4 x ' A' or 'B'
FILTERED AUDIO INPUT SIGNAL
2 x S INPUT
N
R
Figure 5: Measurement of an Rx Frequency 5.2.4.2 The Integer (N) - Byte 1 This is a binary number representing twice the number of complete input audio cycle periods. It is counted during the specified measurement period (t), when (t) is: High Band Decode Mid Band Decode Extended Band Decode = = = 9.125ms 18.250ms 9.125ms
Note: See section 5.2.4.4 for calculation of measurement period (t) using a Xtal other than 4.032MHz.
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MX803A PRELIMINARY INFORMATION
5.2.4.3 The Remainder (R) - Byte 0 This is a binary number representing the remainder part, R, of twice the Input Signal Frequency. R = "the number of specified measuring-clock cycles" required to complete the specified measurement period (See 5.2.4.2). The clock cycle frequency (f) is: High Band Decode Mid Band Decode Extended Band Decode = = = 56.00kHz 28.00kHz 56.00kHz
Note: See section 5.2.4.4 for calculation of clock cycle frequency (f) using a Xtal other than 4.032MHz.
(R)
(R)
(R)
(R)
Figure 6: Format of the Rx Tone Frequency Register 5.2.4.4 fXTAL Scaling Factors The following formulas allow the calculation of the Integer N (see section 5.2.4.2) and the Remainder R (see section 0) using any Xtal value. 4.032 t scaled = t x f XTAL 5.2.5 Frequency Measurement The following formulas show the derivation of the Rx frequency SIN from the measured data bytes (N and R) Note: The following measurements are based on a clock frequency of 4.032 MHz. See section 5.2.4.4 for a scaling formula for other Xtal values. 5.2.5.1 High Band Measurement SIN - High Band In the measurement period of 9.125ms, there are N cycles at 2SIN and R clock cycles at 56.000kHz. N and R - High Band The measurement period = 9.125ms. Clock Frequency = 56.000kHz The measured frequency = 2SINHz In the measurement period there are: 2SIN x 9.125 x 10 -3 cycles NHIGH is the lower integer value of the decimal number: N = INT (9.125 x 10 -3 x 2SIN ) RHIGH is the lower integer value of the decimal number: R = INT (9.125 x 10 - 3 N ) x 56000 2SIN f f scaled = f x XTAL 4.032
N R + = 9.125ms 2SIN 56000 28000 x N (511 - R)
from which SIN =
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MX803A PRELIMINARY INFORMATION
5.2.5.2 Mid Band Measurement SIN - MID Band In the measurement period of 18.250ms, there are N cycles at 2SIN and R clock cycles at 28.000kHz. N and R - High Band The measurement period = 18.250ms. Clock Frequency = 28.000kHz The measured frequency = 2SINHz In the measurement period there are: 2SIN x 18.250 x 10 -3 cycles NMID is the lower integer value of the decimal number: N = INT (18.250 x 10 -3 x 2SIN ) RMID is the lower integer value of the decimal number: R = INT (18.250 x 10 -3 N ) x 28000 2SIN
N R + = 18.250ms 2SIN 28000 14000 x N (511 - R)
from which SIN =
5.2.5.3 Extended Band Measurement SIN - Extended Band In the measurement period of 9.125ms, there are N cycles at 2SIN and R clock cycles at 56.000kHz. N and R - High Band The measurement period = 9.125ms. Clock Frequency = 56.000kHz The measured frequency = 2SINHz In the measurement period there are: 2SIN x 9.125 x 10 -3 cycles NEXTENDED is the lower integer value of the decimal number: N = INT (9.125 x 10 -3 x 2SIN ) REXTENDED is the lower integer value of the decimal number: R = INT (9.125 x 10 - 3 N ) x 56000 2SIN
N R + = 9.125ms 2SIN 56000 28000 x N (511 - R)
from which SIN =
5.2.6 Write to RX Notone Timer Register A/C 33H, followed by 1 byte of Command Data 5.2.6.1 Operation of the RX Notone Timer A NOTONE period is that period when no signal or a consistently bad quality signal is received. The NOTONE Timer is employed to indicate to the C that a NOTONE situation has existed for a predetermined period. The NOTONE Timer period is "primed" by writing to the NOTONE Timer Register (33H) using the instructions and information (1 data byte) given in Table 6. This timer register can be written-to and set in any mode of the MX803A except "Notone Timer Powersave." Priming the timer sets the timing period; this period will not be allowed to start until at least one frequency (tone) measurement has been successfully completed. The NOTONE Timer is a one-shot timer that is reset only by successful tone measurements. If the quality of the received signal drops to an unusable level the NOTONE Timer will start its run-down. On completion of this timer period, the NOTONE Timer Period Expired bit in the Status Register and an Interrupt are set. Upon detection of the Interrupt, the Status Register should be read by the C to ascertain the source of the Interrupt.
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Audio Signaling Processor
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MX803A PRELIMINARY INFORMATION
The NOTONE Timer Period Expired bit is cleared: 1. By a read of the Status Register. 2. New NOTONE Timer Information 3. General Reset Command The timer is set to 00H by a General Reset command.
Setting MSB 7 0 3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 6 0 2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 5 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 4 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Transmitted Bit 7 first these 4 bits must be 0 period (ms) High Band 0 20 40 60 80 100 120 140 160 280 200 220 240 260 280 300 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 % Mid Band 0 40 80 120 160 200 240 280 320 360 400 440 480 520 560 600 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 % Function / Period
Table 6: RX Notone Timer Settings 5.2.6.2 NOTONE TIMER CIRCUITRY The following situations may be encountered by the Notone Timer Circuitry 5.2.6.2.1 No Signal The Notone timer can only start its run down on completion of a valid frequency measurement. 5.2.6.2.2 No signal after a valid Tone measurement The timer will start to run down when the last RX Tone Measurement complete bit is set. At the end of the "primed" period the NOTONE Timer Period Expired bit in the Status Register and the Interrupt will be set. 5.2.6.2.3 Signal fades after a valid Tone measurement The timer will start to run down when the signal becomes unreadable to the device. At the end of the "primed" period the NOTONE Timer Period Expired bit in the Status Register and the Interrupt will be set. 5.2.6.2.4 Signal appears after the Timer has started If the frequency measurement is more than 75% complete when the timer period expires, neither the NOTONE bit nor the Interrupt will be set unless that frequency measurement is subsequently aborted.
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Audio Signaling Processor
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MX803A PRELIMINARY INFORMATION
SIGNAL INPUT SINPUT
Valid Tone
"RX Measure Complete" Set
"RX Measure Complete" Set
"RX Measure Complete" Set
NOTONE TIMER
Timing Period "Primed"
SINPUT
Signal Fades "RX Measure Complete" Set
NOTONE TIMER
Timing Period "Primed" Timing Period "Not Reset" "RX Notone Timer Expired" and Set
SINPUT
Signal Lost and Recovered
"RX Measure Complete" Set
"RX Measure Complete" Set
"RX Measure Complete" Set
NOTONE TIMER
Timing Period "Primed" Timing Period "Reset"
"RX Notone Timer Expired" and Not Set
Figure 7: Notone Timing
5.2.7 Write to General Purpose Timer Register A/C 36H, followed by 1 byte of Command Data 5.2.7.1 Operation of the General Purpose Timer This timer, which is not dedicated to any specific function within the MX803A, can be used within the DBS 800 system to indicate time-elapsed periods of between 10-150ms in the High Band or 20-300ms in the Mid Band to the C. Setting of the timer is by loading a single byte data word via the C-BUS (See Table 7) to the MX803A through the Command Data line. The timer will be reset and the run-down started on completion of Timer Data Word loading. When the programmed time period has expired, the General Purpose Timer Expired bit (bit 2) in the Status Register and the Interrupt are set. The General Purpose Timer Expired bit is cleared: 1. By a read of the Status Register 2. New G/P Timer information 3. General Reset Command.
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Audio Signaling Processor
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MX803A PRELIMINARY INFORMATION
When the programmed time period has expired, this timer will reset, restart itself and continue sequencing until: 1. New G/P Timer information is written 2. A General Reset Command is received. The General Purpose Timer Expired bit and the interrupt will remain set until cleared. The timer is set to 00H (0ms) by a General Reset command.
Setting MSB 7 0 3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 6 0 2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 5 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 4 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Transmitted Bit 7 first these 4 bits must be 0 Reset Timer and Start Timing period (ms) High Band 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 % Mid Band 0 20 40 60 80 100 120 140 160 180 200 220 240 260 280 300 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 % Function / Period
Table 7: General Purpose Timer Settings
5.3 Powersave
Various sections of the MX803A can be placed independently into a power-economical condition. Table 8 gives a summary of these states available to the MX803A. Powersaved Section Tone Encoder 1 Tone Encoder 2 Input Amplifier Instruction Source TX Tone Gen. 1 Reg. (34H) TX Tone Gen. 2 Reg. (35H) All bits = "0" All bits = "0" Table Table 4 Table 5
This action is automatic when both Tone Encoders are in the Powersave condition
Table 8: MX803A Powersave Functions
5.3.1 Powersave Conditions Xtal/Clock and C-BUS: This circuitry is always active, on all DBS 800 ICs, under any depowered/powersaved conditions
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Audio Signaling Processor
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MX803A PRELIMINARY INFORMATION
5.4 Interrupt Request IRQ
An Interrupt (IRQ), when enabled, is provided by the MX803A to indicate the following conditions to the C. Notone Timer Period Expired Enabled Set By control Resister bit 5 When the preset Notone Flag is set By Status Register bit 1 By reading the Status Register G/Purpose Timer Period Expired By control Resister bit 6 When the General Purpose Timer has timed out. By Status Register bit 2 By reading the Status Register Table 9: Interrupt Request On recognition of the "Read Status" Command byte, the interrupt output is cleared, the Status bits are transferred to the C via the C-BUS Reply Data line and the internal Status bits are cleared. Rx Tone Measurement Complete By control Resister bit 5 When an RX Frequency Measurement has been successfully completed By Status Register bit 0 By reading the Status Register
Identified Cleared
5.5 Operational Recommendations
Following initial system power-up, a General Reset command should be sent. 5.5.1 Receive Sequence 1. Send Control Command for RX: Select Midband/Highband and Digital Filter length. 2. Disable transmitters if desired by writing to Tone Frequency registers. 3. Prime the Notone timer by sending the required period byte. 4. Enable/disable interrupts as desired. 5. When a valid tone has been detected by a successfully completed measurement the Status Register is set to "Tone Measurement Complete" and an interrupt is set to the C. 6. The C examines the Status Register. If tone measurement is complete, it reads in the RX Tone Frequency in the form N + R (Figure 6). 7. RX Tone Measurement Complete interrupts are periodically sent to the C unless Notone is detected, in which case a Notone Interrupt is sent. 5.5.2 Transmit Sequence 1. Set Tone Frequency Generators to Notone during the transmitter initialization period. 2. Send Control Command for TX: Select Sum/Switched Sum Out and Audio Switch states. 3. Send General Purpose (GP) Timer information for the Notone transmitter initialization period. This will initiate the timer. 4. Enable/disable interrupts as desired. 5. C waits for "GP Timer Expired," reads the Status Register to check interrupts due to timer, and resets the Status Bit. If required, the C sends the next timer period followed by the next tone(s) frequency information. A new timer period sent will reset the timer, otherwise the timer is self-resetting. 6. The C monitors the interrupts and repeats steps 5 and 6 as required. 7. After last loaded tone, C turns off Tone Generator(s).
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Audio Signaling Processor
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MX803A PRELIMINARY INFORMATION
5.6 General Reset
Upon power-up the bits in the MX803A registers will be random (either "0" or "1"). A General Reset Command (01H) will be required to reset all microcircuits on the C-BUS. It has the following effect on the MX803A: Control Register Status Register (bits 0, 1, 2) Notone Timer Tone Gen. 1 Reg. (2 bytes) Tone Gen. 2 Reg. (2 bytes) Gen. Purpose Reg. Set as 00H Set as 00H Set as 00H Set as 0000H Set as 0000H Set as 00H
Table 10: General Reset effect on MX803A This sets the MX803A to Encoder High Band (625Hz to 3000Hz) with interrupts disabled and both timers set to 00H. Both timers should be set up before interrupts are enabled to prevent initial, undesired interrupts.
6. Timing Information
Figure 8 shows timing parameters for two-way communication between the C and the MX803A on the C-BUS.
tCSOFF
CHIP SELECT
tNXT
SERIAL CLOCK
tNXT
tNXT
tCSE
tCK
COMMAND DATA
7
MSB
6
5
4
3
2
1
0
LSB
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
ADDRESS/COMMAND BYTE REPLY DATA
FIRST DATA BYTE
LAST DATA BYTE
tHIZ
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
LSB MSB FIRST REPLY DATA BYTE
Logic level is not important
LAST REPLY DATA BYTE
Figure 8: C-BUS Timing
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Audio Signaling Processor
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MX803A PRELIMINARY INFORMATION
Parameter tCSE tCSH tCSOFF tNXT tCK tCH tCL tCDS tCDH tRDS tRDH tHIZ Chip Select Low to First Serial Clock Rising Edge Last Serial Clock Rising Edge to Chip Select High Chip Select High Command Data Inter-Byte Time Serial Clock Period Decoder or Encoder Clock High Decoder or Encoder Clock Low Command Data Set-Up Time Command Data Hold Time Reply Data Set-Up Time Reply Data Hold Time Chip Select High to Reply Data High - Z
Min 2.0 4.0 2.0 4.0 2.0 500 500 250 0 250 50.0
Typ
Max
Unit s s s s s ns ns ns ns ns ns s
2.0
Table 11: Timing Information Timing Information Notes 1. Command Data is transmitted to the peripheral MSB (bit 7) first, LSB (bit 0) last. Reply Data is read from the MX803A MSB (bit 7) first, LSB (bit 0) last. 2. Data is clocked into the MX803A and into the C on the rising Serial Clock edge. 3. Loaded data instructions are acted upon at the end of each individual, loaded byte. 4. To allow for differing C serial interface formats, the MX803A will work with either polarity Serial Clock pulses.
t CK t CL t CH t CDH t CDS
COMMAND DATA (from C) SERIAL CLOCK (from C)
70% VDD 30% VDD
t RDS
REPLY DATA (to C)
t RDH
Figure 9: Timing Relationship for C-BUS Information Transfer
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Audio Signaling Processor
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MX803A PRELIMINARY INFORMATION
7. Performance Specification
7.1 Electrical Performance
Absolute Maximum Ratings Exceeding these maximum ratings can result in damage to the device. Operation of the device outside of the operating limits is not suggested. General Supply Voltage (VDD - VSS) Voltage on any pin to VSS Current VDD VSS Any other pins DW / J / LH Packages Operating Temperature Storage Temperature Total allowable Power Dissipation at TAMB = 25C Derating above 25C Operating Limits All devices were measured under the following conditions unless otherwise noted. Notes Supply (VDD-VSS) Temperature Xtal/Clock Frequency Min. 4.5 -40 Max. 5.5 85 4.0 Units V C MHz -40 -55 85 125 800 10 C C mW mW/C above 25C -30 -30 -20 30 30 20 mA mA mA Min. -0.3 -0.3 Max. 7.0 VDD + 0.3 Units V V
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Audio Signaling Processor
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MX803A PRELIMINARY INFORMATION
Operating Characteristics For the following conditions unless otherwise specified: VDD = 5.0 @ TAMB = 25C Xtal = 4MHz (refer to section 5.2.4.4 for Xtal Scaling factor) Audio level 0dB ref. = 308mVRMS @ 1kHz (60% deviation, FM) Noise Bandwidth = 5.0kHz Band-Limited Gaussian Notes Static Values Supply Voltage Supply Current Decoder + Both Timers Decoder, Both Timers + One TX only All Functions Enabled Analog Impedance RX Audio Input Summing Amp Input Switch Tones 1 and 2 Outputs CAL/CUES Output Summing Outputs Dynamic Values Digital Interface Input Logic "1" Input Logic "0" Output Logic "1" (IOH = -120A) Output Logic "0" (IOL = 360A) IOUT Tristate (Logic "1" or "0") Input Capacitance IOX (VOUT = 5V) Overall Performances RX - Decoding High Band Sensitivity Tone Response Time Good Signal Tone-to-Noise Ratio = 0dB Frequency Band Measurement Resolution Measurement Accuracy 9 625 0.2 0.5 3000 Hz % % 5,10 5,6,10 30.0 40.0 ms ms -20.0 dB 1 1 2 3 3 1 4 4.6 0.4 4.0 7.5 4.0 3.5 1.5 V V V V A pF A 20.0 20.0 1.0 10.0 5.0 10.0 M M k k k k 2.0 4.0 5.0 mA mA mA 4.5 5.0 5.5 V Min. Typ. Max. Units
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Audio Signaling Processor
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MX803A PRELIMINARY INFORMATION
Notes Mid-Band Sensitivity Tone Response Time Good Signal Tone-to-Noise Ratio = 0dB Frequency Band Measurement Resolution Measurement Accuracy Extended Band Sensitivity Tone Response Time Good Signal Frequency Band Measurement Resolution Measurement Accuracy TX - Encoders 1 and 2 Tone Frequency Period (1/fTONE) Error Tone Amplitude Total Harmonic Distortion Rise Time to 90% Fall Time to 10% Frequency Change Time Timers General Purpose Timing Period Range High-Band Mid-Band RX Notone Timing Period Range Hi-Band Mid-Band Xtal/Clock Frequency (fXTAL) 8 9 5,10 9 7,10 6,7,10
Min.
Typ. -20.0
Max.
Units dB
60.0 80.0 313 0.2 0.5 -20.0 20.0 1250 0.2 0.5 208 -1.5 3/fTONE 5.0 3/fTONE 3000 1.0 1.5 5.0 6000 1500
ms ms Hz % % dB ms Hz % % Hz s dB % ms ms ms
10.0 20.0
150 300
ms ms
20.0 40.0 4.0
300 600 6.0
ms ms MHz
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Audio Signaling Processor
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MX803A PRELIMINARY INFORMATION
Operating Characteristics Notes: 1. Device control pins: Serial Clock, Command Data, and CS . 2. Reply Data output. 3. Reply Data and IRQ outputs. 4. Leakage current into the "Off" IRQ output. 5. Measurement period = 9.198ms. 6. Decode Probability = 0.993. 7. Measurement period = 18.396ms. 8. When set to Powersave. 9. For a good input signal. 10. Inversely proportional to Xtal frequency, i.e. Spec. x becomes 20ms. 4MHz . So, for a 6MHz clock a 30ms tone response time f XTAL
7.2 Packaging
Package Tolerances
A Z B E W L PIN 1 X Y CK H J P T
DIM. A B C E H J K L P T W X Y Z MIN.
0.597 (15.16) 0.286 (7.26) 0.093 (2.36) 0.390 (9.90) 0.003 (0.08) 0.013 (0.33) 0.036 (0.91)
TYP.
MAX.
0.613 (15.57) 0.299 (7.59) 0.105 (2.67) 0.419 (10.64) 0.020 (0.51) 0.020 (0.51) 0.046 (1.17)
ALTERNATIVE PIN LOCATION MARKING
0.050 (1.27) 0.016 (0.41) 0.050 (1.27) 0.009 (0.23) 45 0 5 5 10 7 0.0125 (0.32)
NOTE : All dimensions in inches (mm.) Angles are in degrees
Figure 10: 24-pin SOIC Mechanical Outline: order as part no. MX803ADW
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MX803A PRELIMINARY INFORMATION
E B Y DA
W
C K J W T H
Package Tolerances
DIM. A B C D E F G H J K P T W Y MIN. TYP. MAX.
0.380 (9.61) 0.409 (10.40) 0.380 (9.61) 0.409 (10.40) 0.128 (3.25) 0.146 (3.70) 0.417 (10.60) 0.435 (11.05) 0.417 (10.60) 0.435 (11.05) 0.250 (6.35) 0.250 (6.35) 0.023 (0.58) 0.018 (0.45) 0.022 (0.55) 0.047 (1.19) 0.048 (1.22) 0.049 (1.24) 0.051 (1.30) 0.006 (0.152) 0.009 (0.22) 45 30 6
PIN 1 P
G F
NOTE : All dimensions in inches (mm.) Angles are in degrees
Figure 11: 24-pin PLCC Mechanical Outline: order as part no. MX803ALH
A
Package Tolerances
DIM. MIN. TYP. MAX. A B C E E1 F H J J1 K K1 L P T
1.240 (31.50) 1.260 (32.00) 0.514 (13.06) 0.583 (14.79) 0.165 (4.19) 0.230 (5.84) 0.600 (15.23) 0.670 (17.00) 0.594 (15.09) 0.615 (15.61) 1.100 (27.94) 0.02 (0.51) 0.018 (0.46) 0.055 (1.39) 0.050 (1.27) 0.080 (2.03) 0.074 (1.88) 0.080 (2.03) 0.115 (2.92) 0.200 (5.08) 0.10 (2.54) 0.0106 (0.269) 0.0094 (0.239)
B
E1
E
PIN1 K H L J J1 F P K1 C
T
NOTE : All dimensions in inches (mm.) Angles are in degrees
Figure 12: 24-pin CDIP Mechanical Outline: order as part no. MX803AJ
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